FPGA modules

This Page has been set up to allow the distribution of Altera CPLD and FPGA Mega Functions.

All of these modules are "plug a play" and should fit easily into any project. They do, however, require some basic support by their host system to operate correctly.

Some modules are here to replace obsolete chips, while others were created for projects that needed them.

INMOS "OS-Link" adapter

Download OS-Link Mega-Function

INMOS^tm have long since obsolete their "C012" and "C011" Link Adapter chips along with the Transputer's they connected to. However, the ST20's still have an "OS-link" and they can be connected to one of these obsolete devices.

This mega-function can be compiled into a CPLD or FPGA to perform the same operations. It provides a register set and bit set compatible with the original, making it transparent to software. See INMOS data sheets for programming information.

Its clock source should be equal to twice the bit rate. For example:

10MHz	5Mbps
20MHz	10Mbps
40MHz	20Mbs

Reg 0	Bit-7..0	Receive data register
Reg 1	Bit-7..0	Transmit data register
Reg 2	Bit-0	1=Rx Full, 0=No data Rx'ed
	Bit-1	1=Rx interrupt enabled
Reg 3	Bit-0	1=Tx full, 0=Tx empty
	Bit-1	1=Tx interrupt enabled

Addition uses for this UART can be many. It is a UART with built in handshaking that can work to very high speeds. This makes a good for short haul inter-computer communications. Either computer does not have to be a Transputer for this to work.

Basic UART with "OS-Link" registers

Download the Basic UART Mega-Function

This is a basic UART (no FIFO's) that can send and receive data at any bit rate. The format is fixed to 8 bits, no parity, 2 stop bits.

The registers are laid out the same as the INMOS OS-link Mega Function along with the main control bits. However, there are additional control bits out side the standard set to allow for additional functions.

This is a register-bit description:

Reg 0	Bit-7..0	Receive data register
Reg 1	Bit-7..0	Transmit data register
Reg 2	Bit-0	1=Rx Full, 0=No data Rx'ed
	Bit-1	1=Rx interrupt enabled
	Bit-2	Not used
	Bit-5..3	Speed select:
	0x00	Clock / 16
	0x08	Clock / 32
	0x10	Clock / 64
	0x18	Clock / 128
	0x20	Clock / 256
	0x28	Clock / 512
	0x30	Clock / 1024
	0x38	Clock / 2048
Reg 3	Bit-0	1=Tx full, 0=Tx empty
	Bit-1	1=Tx interrupt enabled
	Bit-2	0=Tx logic enabled

9-bit Fast Counter

Download 9-bit Fast Counter

A 9-bit counter that ensures all outputs change to their correct state at the same time.

It is a straight forward 9-bit UP counter with minimal inputs to ease requirements made of the designer.

10-bit Fast Counter

Download 10-bit Fast Counter

A 10-bit counter that ensures all outputs change to their correct state at the same time.

It is a straight forward 10-bit UP counter with minimal inputs to ease requirements made of the designer.

8-bit Programmable Fast Counter

Download 8-bit Programmable Fast Counter

An 8-bit Fast Counter which can be loaded with a starting count. The outputs will change to their correct state at the rising edge of "CLK" input.

A new count is transferred to the counter on the rising edge of "LOAD" input signal, which can happen at any time.

It is a straight forward 8-bit programmable UP counter with minimal inputs to ease requirements made of the designer.

9-bit Programmable Fast Counter

Download 9-bit Programmable Fast Counter

A 9-bit Fast Counter which can be loaded with a starting count. The outputs will change to their correct state at the rising edge of "CLK" input.

A new count is transferred to the counter on the rising edge of "LOAD" input signal, which can happen at any time.

It is a straight forward 9-bit programmable UP counter with minimal inputs to ease requirements made of the designer.

10-bit Programmable Fast Counter

Download 10-bit Programmable Fast Counter

A 10-bit Fast Counter which can be loaded with a starting count. The outputs will change to their correct state at the rising edge of "CLK" input.

A new count is transferred to the counter on the rising edge of "LOAD" input signal, which can happen at any time.

It is a straight forward 10-bit programmable UP counter with minimal inputs to ease requirements made of the designer.

20-bit Shift Register

Click here to download
(148KB ZIP)

This is a 20-bit shift register suitable for connecting directly to an Allegro ™ "5812" VFD driver. It has a 20-bit shift register, holding latch, and VFD driver stage making it a requirement that a large shift register must source data to it.

This mega function is used by the VFD Controller mega function to produce a complete VFD solution.

INMOS B004 Transputer ISA Card

Click here to download
(15KB ZIP)

STMicroelectronics ^(tm) obsolete their IMSC011 & IMSC012 Link Adapter chips around the end of 1998. This caused a problem for people still using the part. And to make matters worse, the ST20TP4 microprocessor, still in production, supports a similar UART.

This solution replaces all the 80x86 ISA interfacing logic and INMOS Link Adapter by synthesising it into a single CPLD.

The supplied files will compile using Altera's "Baseline" tools, and all pin outs from the chip have been set to dynamic allocation. You may want to statically set them.

Its master clock also changes from 5MHz to a more fundamental setting since it is difficult to synthesis an accurate clock multiplier in FPGA:
5Mbps	10MHz
10Mbps	20MHz
20Mbps	40MHz

11 Digit Vacuum Fluorescent Display Controller

Click here to download Mega Function
(140KB ZIP)

Click here to see example 11 Digit VFD schematic diagram
(71KB PDF)

Click here to download Data Sheet bundle
(1706KB ZIP)

Click here to download CPLD project for 11 Digit VFD hardware
(312KB ZIP)

On this web site an Allegro "5812" VFD driver is used to control a VFD tube. As such a small micro-controller, such as the Zilog z8 is usually programmed to serialise segment and grid controls to be sent to it.

However, this mega function can do the same job using a CPLD or FPGA. Migrating the concepts to hardware makes the whole process faster, simpler and more efficient. Any micro-controller attached to the PLD can concentrate on its more complex work rather than maintaining VFD multiplexing.

An example of the hardware that supports all this is also provided as "CPLD 11 Digit VFD Counter" schematic, and CPLD project. From it an idea of how to use the Mega Function can be easily gained.

The Mega Function controls are simple and fairly obvious. All user documentation is contained in the download files to help in new designs.

Please take note of the "5812" pin assignment requirement.