VGA6800 FPGA Detailed Information

VGA6800 is a Video Graphics Adapter resolution video controller suited to integration with 8-bit microprocessors and small embedded controllers. The interface between the two is efficient enough to allow it to happen, even though small systems have limited resources.

The best way to understand how a small microprocessor can drive a VGA video controller is to read the VGA6800 Programmers Manual. It will explain many of the hardware support mechanism that make it all happen.

This screen shot will give an idea of the video image generated. The alpha-numerical font at the top centre of the screen is a fixed type 16 pixels wide by 8 lines high. Each of the characters have been "blitted" to the screen along with the test counter at the bottom right of the screen.

The cross hatch line grid shows the horizontal and vertical line drawing hardware in action, while the colour bars demonstrate the hardware rectangle fill drawing.

The White rectangle behind the Red, Green and Blue colour bars is actually an alternating white-black-white pattern. Not a full white as it may appear

VGA6800 uses the digital video colour method, meaning that each colour can either be turned on or off and nothing in between. This limits the number of displayable colours to eight with no gradients in between. As a result only three bits are needed for each pixel that allows two pixels to be packed into each VRAM byte.

Video screen dimension is 640 pixels wide by 480 lines down resulting in a total VRAM foot print of 256KB while up to eight video pages can be flipped in to view as needed.

A single 512KB, or 2MB, standard CMOS Static RAM (SRAM) is used as VRAM keeping cost and PCB real estate down. Therefore video refresh data is interleaved with CPU access data. The hardware does it efficiently using all available bus idle time for drawing operations as needed.

Hardware drawing works at full speed, in between video line reads, in an automatic mode. The CPU does not need to know how graphics operations are done, it just knows when they are finished.

The prototype is shown here to provide an idea of the intentions behind the supplied programming file and schematics.

This arrangement demonstrates the Altera University Program CPLD & FPGA development board (left) method of connection to an M6800 8-bit system (right).

If you have the Altera board you can try out the SOF file immediately.

Please note that the SOF file is compiled for a Flex10K20 FPGA that is fitted to the "U1" version of the Altera development board. Their next version "U2" uses a Flex10K70 FPGA making the supplied SOF file incompatible.

The possible benefits of VGA6800 is many, however, by coupling the VGA6800 video controller with a soft-core CPU allows an entire system to be integrated into a single FPGA chip: a System-On-a-Chip "SOC".

From this It is possible to produce extremely small systems to act as information terminals or control consoles from the smallest micro controllers.